By M.C. Bhuvaneswari
This ebook describes how evolutionary algorithms (EA), together with genetic algorithms (GA) and particle swarm optimization (PSO) can be used for fixing multi-objective optimization difficulties within the quarter of embedded and VLSI approach layout. Many advanced engineering optimization difficulties could be modelled as multi-objective formulations. This booklet presents an advent to multi-objective optimization utilizing meta-heuristic algorithms, GA and PSO and the way they are often utilized to difficulties like hardware/software partitioning in embedded platforms, circuit partitioning in VLSI, layout of operational amplifiers in analog VLSI, layout house exploration in high-level synthesis, hold up fault trying out in VLSI trying out and scheduling in heterogeneous disbursed structures. it truly is proven how, in each one case, many of the elements of the EA, specifically its illustration and operators like crossover, mutation, and so forth, will be individually formulated to unravel those difficulties. This publication is meant for layout engineers and researchers within the box of VLSI and embedded approach layout. The publication introduces the multi-objective GA and PSO in an easy and simply comprehensible manner that might entice introductory readers.
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Extra info for Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems
The balance of exploration and exploitation helps the hybrid NSPSO in obtaining good-quality solutions. In PSO, the set of solutions in pbest is the optimal Pareto solution found during the searching procedure. The pbest solutions are employed to guide the evolution of the particles in the next iteration. In the hybrid NSPSO algorithm, PHC procedure is employed to a selected number of pbest solutions belonging to various fronts. The PHC procedure used employs a mutation operation to generate a neighborhood for each solution subject to PHC procedure.
NSGA-II obtains the Pareto-optimal solutions faster than WSGA and MOPSO-CD. References Al-Abaji RH (2002) Evolutionary techniques for multi-objective VLSI net list partitioning. Dissertation, King Fahd University of Petroleum and Minerals, Dhahran, Kingdom of Saudi Arabia Ababei C, Selvakumaran N, Bazargan K, Karypis G (2002) Multi objective circuit partitioning for cut size and path-based delay minimization. In: Proceedings of the 2002 IEEE/ACM international conference on computer-aided design, 10–14 Nov, Sanjose, USA, pp 181–185 Areibi S, Vannelli A (1993) A combined eigenvector tabu search approach for circuit partitioning.
2. Each task (node) in the DAG is associated with SW area and SW time. The SW area (CS) represents the SW memory utilized by the task and SW time (tS) represents the execution time of the task if implemented in software processor. The HW implementation of each task is associated with an HW area and an HW time. The HW area (CH) represents the area occupied by the task while implementing in HW and the HW time (tH) is the execution time of the task if implemented in HW. If one of the two communicating tasks is implemented in HW, and the other in SW processor, then the communication cost (CC) between them incurs a significant overhead and is considered during partitioning.
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